This invention relates generally to logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like and, more particularly, to logic elements that are rendered non-volatile by the addition of ferroelectric capacitors and supporting circuitry.
Integrated circuits can be divided into analog functions and digital functions. Most digital functions can be implemented using the following elements: combinatorial logic, clocked registers and memory. Until recently, a clear distinction was made between volatile memories such as SRAM and DRAM and non-volatile memories such as ROM, EPROM, EEPROM and Flash EEPROM. Volatile memories offer high speed and high density, but they lose data when the power supply is removed. Non-volatile memories, on the other hand, keep their data when the power supply is removed and offer relatively high density, but write times and write endurance are limited.
Today, ferroelectric memories are commercially available that provide non-volatility while retaining write performance similar to that of volatile memories. So, as ferroelectric memory technology continues to advance, the gap between volatile and non-volatile memory will continue to shrink.
Another gap exists between clocked registers and memory. Fundamentally, clocked registers, such as the multiple-purpose registers used in microcontrollers and microprocessors, are low-density memories combined with combinatorial logic in such a way as to create the desired register function. Because of the relatively late development of non-volatile memory and its poor write speed performance relative to volatile memories, clocked registers have always been volatile and most often based on cross-coupled devices similar to an SRAM cell.
Conversely, floating-gate memories require high currents to program each bit, each bit takes a long time to program, and current sensing is used to determine the state of the cell. In the current logic system design paradigm, data requiring non-volatility must either be backed up by a battery or stored in a low-write-speed non-volatile memory and restored byte-by-byte on power-up.
What is desired, therefore, is a class of logic circuits that retain the functionality and operating characteristics found in present-day integrated circuit versions of these logic circuits, while introducing the further benefit of non-volatility.
According to the present invention, the following description details the methodology used to render logic elements non-volatile through the strategic addition of ferroelectric capacitors and supporting devices. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance. More so than the fundamental logic elements involved, memory sense amplifiers require carefully balanced layout to properly detect the memory state over the lifetime of the part. Because of this, care is taken to create symmetry within the design that is easily translated into device layout.
The recent availability of high performance ferroelectric non-volatile memory opens up the possibility of a new type of system design wherein registers are made non-volatile. The new paradigm involves making the register itself non-volatile through the use of ferroelectric memory technology. In this way, the status of some or all registers can be restored simultaneously on power-up.
Ferroelectric memory technology allows the reading or writing of thousands of bits or more simultaneously due to the polarization-based storage mechanism, fast write times and voltage sensing.
At the present time, reliable ferroelectric memories employ controlled timing sequences during read and write operations. While all the circuits presented below theoretically function for any sensing speed and any non-zero ferroelectric capacitor interrogation time, the examples presented use currently standard interrogation and sensing approaches. Where timing diagrams are shown, they may not represent the only useful means of interrogation and sensing.
Finally, ferroelectric memories have shown sensitivity to the ratio of the load capacitance to the effective capacitance of the switching capacitor. This ratio is commonly called the bit/cell ratio. In arrayed ferroelectric memories, the load capacitance due to parasitic terms such as source/drain diffusions and metal-substrate capacitance is often sufficient to meet the desired performance parameters. In some low-density memories, the parasitic load capacitance is not sufficient to create the desired bit/cell ratio. In this case, extra discrete load capacitors can be added. Because ferroelectric memories already have a high dielectric material available, the added load capacitance may be derived from ferroelectric load capacitors. In the case of non-volatile logic, the parasitic load capacitance is negligible when compared to the capacitance of the ferroelectric storage capacitor. As such, the incorporation of extra load capacitance is required. Previous non-volatile logic work makes no mention of this required load capacitance.
In a first embodiment of the invention, a ferroelectric, non-volatile, SR flip-flop includes a set input, a reset input, a Q output, a complementary Q output, a first NAND gate having an internal circuit node, a first input coupled to the set input, a second input coupled to the output, and an output coupled to the complementary Q output, a second NAND gate having an internal circuit node, a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output, and a ferroelectric capacitor circuit coupled between the internal node of the first NAND gate and the internal node of the second NAND gate.
The first NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a voltage source, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the voltage source, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to ground.
Alternatively, the first NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a first controlled power supply, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the first controlled power supply, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to a second controlled power supply.
The second NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a voltage source, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the voltage source, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to ground.
Alternatively, the second NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a first controlled power supply, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the first controlled power supply, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to a second controlled power supply.
The ferroelectric capacitor circuit for the first and additional embodiments includes a first ferroelectric capacitor coupled between the internal circuit node of the first NAND gate and ground, a second ferroelectric capacitor coupled between the internal circuit node of the second NAND gate and ground, and a ferroelectric capacitor circuit coupled between the internal circuit nodes of the first and second NAND gates, which can be formed of serially-coupled matched ferroelectric capacitors coupled together at a common plate node. The ferroelectric capacitor circuit can be selectively coupled to the internal nodes of the first and second NAND gates.
The SR flip-flop of the first embodiment as well as additional embodiments optionally includes a precharge circuit, an equalization circuit, a gate control circuit and/or an internal drive isolation circuit.
In a second embodiment of the invention, a ferroelectric, non-volatile, SR flip-flop includes a set input, a reset input, a Q output, a complementary Q output, a first NOR gate having an internal circuit node, a first input coupled to the set input, a second input coupled to the output, and an output coupled to the complementary Q output, a second NOR gate having an internal circuit node, a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output, and a ferroelectric capacitor circuit coupled between the internal node of the first NOR gate and the internal node of the second NOR gate.
The first NOR gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a voltage source, and a drain coupled to the internal node, a second P-channel transistor having a gate coupled to the second input, a source coupled to the internal node, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the first input, and a source coupled to ground, and a second N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to ground.
The first NOR gate optionally includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a first controlled power supply, and a drain coupled to the internal circuit node, a second P-channel transistor having a gate coupled to the second input, a source coupled to the internal circuit node, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the first input, and a source coupled to a second controlled power supply, and a second N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the second controlled power supply.
The second NOR gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a voltage source, and a drain coupled to the internal circuit node, a second P-channel transistor having a gate coupled to the second input, a source coupled to the internal circuit node, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the first input, and a source coupled to ground, and a second N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to ground.
The second NOR gate optionally includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a first controlled power supply, and a drain coupled to the internal circuit node, a second P-channel transistor having a gate coupled to the second input, a source coupled to the internal circuit node, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the first input, and a source coupled to a second controlled power supply, and a second N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the second controlled power supply.
In a third embodiment a ferroelectric, non-volatile, JK flip-flop includes a J input, a K input, a Q output, a complementary Q output, a ferroelectric, non-volatile SR flip-flop including a set input, a reset input, a Q output coupled to the Q output of the JK flip-flop, and a complementary Q output coupled to the complementary Q output of the JK flip-flop, a first NAND gate having a first input coupled to the Q output of the JK flip-flop, a second input coupled to the K input, a third input for receiving a clock signal and an output coupled to the set input, and a second NAND gate having a first input for receiving the clock signal, a second input coupled to the J input, a third input coupled to the complementary Q output of the JK flip-flop.
The SR flip-flop can include either a NAND-gate based flip-flop, or a NOR-gate based flip-flop, either of which can be powered by conventional or controlled power supplies.
In a fourth embodiment, a ferroelectric, non-volatile, master-slave JK flip-flop includes a J input, a K input, a Q output, a complementary Q output, a clock input, a complementary clock input, a ferroelectric, non-volatile master JK flip-flop for receiving the J, K, and clock inputs, and having a Q output and a complementary Q output, a slave JK flip-flop coupled to the complementary clock input, and the Q and complementary Q outputs of the master JK flip-flop, and having a Q output coupled to the Q output of the master-slave JK flip-flop and a complementary Q output coupled to the complementary Q output of the master-slave JK flip-flop.
The master and slave flip-flops can include either NAND-gate based flip-flops or NOR-gate based flip-flops, and can be powered either by conventional or controlled power supplies.
In a fifth embodiment, a ferroelectric, non-volatile, D-type flip-flop includes a D input, a Q output, a clocked transmission-gate based master stage having inputs coupled to the D input, and an output, and a ferroelectric, non-volatile, transmission-gate based slave stage having an input coupled to the output of the master stage, and an output coupled to the Q output. The slave stage includes a first clocked transmission gate having an input forming the input of the slave stage and an output, a first controlled inverter having an input coupled to the output of the first clocked transmission gate, and an output, a first non-clocked transmission gate having an input coupled to the output of the first controlled inverter and an output coupled to the output of the slave stage, a second clocked transmission gate having an input, and an output coupled to the output of the first clock transmission gate, a second controlled inverter having an input coupled to the output of the slave stage, and an output coupled to the input of the second clocked transmission gate, a second non-clocked transmission gate having an input coupled to the output of the slave stage and an output coupled to ground, and a ferroelectric capacitor circuit coupled between the output of the first clocked transmission gate and the output of the slave stage. The D-type flip-flop of the fifth embodiment can include optional asychronous set and clear inputs.
In a sixth embodiment, a ferroelectric, non-volatile, D-type flip-flop includes a D input, a Q output, a ferroelectric, non-volatile, transmission-gate based master stage having an input coupled to the D input, and an output, and a clocked transmission-gate based slave stage having an input coupled to the output of the master stage, and an output coupled to the Q output. The master stage includes a first clocked transmission gate having an input forming the input of the master stage and an output, a first controlled inverter having an input coupled to the output of the first clocked transmission gate, and an output, a first non-clocked transmission gate having an input coupled to the output of the first controlled inverter and an output coupled to the output of the master stage, a second clocked transmission gate having an input, and an output coupled to the output of the first clocked transmission gate, a second controlled inverter having an input coupled to the output of the master stage, and an output coupled to the input of the second clocked transmission gate, and a ferroelectric capacitor circuit coupled between the output of the first clocked transmission gate and the output of the master stage. The D-type flip-flop of the sixth embodiment further can include optional asychronous set and clear inputs.
In a seventh embodiment, an N-bit non-volatile serial-in, serial-out shift register includes N ferroelectric, non-volatile D-type flip-flops each having a D input, a Q output, a clock input, and a ferroelectric control input, wherein the D input of a first flip-flop forms the shift register input, the Q output of an Nth flip-flop forms the shift register output, the Q output of an (Nxe2x88x921)th flip-flop is coupled to the input of an Nth flip-flop such that all of the flip-flops are serially coupled together, the clock inputs of each of the flip-flops are coupled together and to a clock bus, and the ferroelectric control inputs of each of the flip-flops are coupled together and to a ferroelectric control bus. In a preferred embodiment N is equal to eight.
In an eighth embodiment, an N-bit non-volatile parallel-in, serial-out shift register includes N multiplexers each having a first input, a second input, a select input, and an output, and N ferroelectric, non-volatile D-type flip-flops each having a D input, a Q output, a clock input, and a ferroelectric control input, wherein the output of an Nth multiplexer being coupled to the D input of an Nth flip-flop, the Q output of an Nth flip-flop being coupled to the first input of an (N+1)th multiplexer, such that all of the multiplexers and flip-flops are coupled together, the clock inputs of each of the flip-flops are coupled together and to a clock bus, the ferroelectric control inputs of each of the flip-flops are coupled together and to a ferroelectric control bus, the second inputs of each of the multiplexers form a parallel input, the select inputs of each of the multiplexers are coupled together and to a select bus, and the Q output of a last flip-flop forms a serial output. In a preferred embodiment N is equal to four.
The foregoing and other objects, features, and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.